1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and driving method thereof.
2. Discussion of the Related Art
Generally, a liquid crystal display (LCD) device displays a picture corresponding to a video signal (i.e., “data voltage”) using a display unit having a plurality of pixels defined by gate and data lines crossing with each other. Each pixel of the display unit consists of a liquid crystal cell adjusting light transmittance according to a corresponding data voltage. A thin film transistor (TFT) acts as a switching device to supply a data voltage from a data line to the liquid crystal cell. The LCD device also includes a gate driver for driving the gate lines and a data driver for driving the data lines. In a liquid crystal panel where the TFT is formed of polysilicon having high electric charge mobility, the gate and data drivers are built in the liquid crystal panel. In such a case, a demultiplexer unit is provided between the data driver unit and the display unit. The demultiplexer unit connects a plurality of data lines to one output line of the data driver, thereby reducing a required number of drive ICs (integrated circuit) needed to configure the data driver.
An LCD device provided with a demultiplexer unit according to a related art is explained with reference to the attached drawings as follows. FIG. 1 shows a block diagram of an LCD device according to a related art.
As shown in FIG. 1, an LCD device according to the related art includes of a display unit 111 on which m-gate lines GL1 to GLm and n-data lines DL1 to DLn perpendicularly cross each other to form (m×n) pixels arranged in a matrix form. A TFT is provided at each intersection of the gate and data lines. A gate driver 101 provides a scan pulse voltage SP to the gate lines GL1 to GLm and a data driver 102 supplies data voltages VD1 to VDk to the data lines DL1 to DLn of the display unit 111. A demultiplexer unit 105 is connected between the display unit 111 and the data driver 102, and a timing controller 106 controls the gate driver 101, the data driver 102, and the demultiplexer unit 105.
The timing controller 106 generates a plurality of control signals to control the drive timing of the gate and data drivers 101 and 102 and aligns pixel data to be applied to the data driver 102. Further, the timing controller 106 generates a plurality of control signals to control the demultiplexer unit 105.
The data driver 102 has a number of output lines OL1 to OLk connected to the output pins (not shown) of the data driver 102. The number of output pins (k) is equal to the number of output lines OL1 to OLk. However, the number of output lines OL1 to OLk connected between the data driver 102 and the demultiplexer unit 105 is smaller than a number of the data lines DL1 to DLn. The demultiplexer unit 105 is explained in detail as follows.
FIG. 2 shows a detailed schematic diagram of the demultiplexer unit 105 shown in FIG. 1. FIG. 3 shows a diagram of drive waveforms of a first demultiplexer DEMUX1 shown in FIG. 2 during a random horizontal sync interval.
As shown in FIG. 2, the demultiplexer unit 105 includes k-demultiplexers DMUX1 to DEMUXk connected between the data driver unit 102 and n-data lines DL1 to DLn of the display unit 111. Each of the demultiplexers DEMUX1 to DEMUXk includes first to third switching devices SW1 to SW3 connected in parallel to one output line OLk and to three of the data lines DL1 to DLn, respectively. The first to third switching devices SW1 to SW3 are turned on at different times in one horizontal period by first to third control signals C1 to C3 supplied from the timing controller 106, respectively. The gate driver 101 sequentially supplies a scan pulse voltage SP to m-gate lines GL1 to GLm during one frame. As shown in FIG. 3, a gate high voltage VGH, which is a high logic voltage of the scan pulse voltage SP, is maintained to drive a corresponding gate line during one horizontal sync period. In this case, the gate high voltage VGH is set to a voltage level that is greater than a threshold voltage of the TFT. Conversely, a gate low voltage VGL is a low logic voltage of the scan pulse voltage SP set as an off-voltage of the TFT.
During a horizontal sync period Hi of driving a selected gate line, the data driver 102 sequentially supplies k-data voltages VD1 to VDk to k-output lines OL1 to OLk connected to the k-demultiplexers DEMUX1 to DEMUXk, respectively. The k-data voltages VD1 to VDk supplied to the k-demultiplexers DEMUX1 to DEMUXk are synchronized with the first to third control signals C1 to C3 from the timing controller 106 to supply three data voltages from each of the k-data voltages VD1 to VDk to the three data lines connected to each of the demultiplexers DEMUX1 to DEMUXk to supply data signals to the n-data lines DL1 to DLn.
More specifically, in each of the k-demultiplexers DEMUX1 to DEMUXk, a gate electrode of the first switching device SW1 is connected to a signal input line IL of the first control signal C1. Likewise, a gate electrode of the second switching device SW2 is connected to a signal input line IL of the second control signal C2, and a gate electrode of the third switching device SW3 is connected to a signal input line IL of the third control signal C3. Hence, when the first to third control signals C1 to C3, as shown in FIG. 3, are sequentially shifted to a high state in one horizontal sync period Hi, the first to third switching devices SW1 to SW3 of each of the demultiplexers DEMUX1 to DEMUXk are driven in sequence from of the first switching device SW1 to the third switching device SW3. The data driver 102 sequentially outputs the corresponding data voltages VD1 to VDk to correspond to the drive sequence of the first to third switching devices SW1 to SW3. As a result, the first demultiplexer DEMUX1, as shown in FIG. 3, sequentially supplies the data voltage for R (red) to the first data line DL1 via the first switching device SW1, the data voltage for G (green) to the second data line DL2 via the second switching device SW2, and the data voltage for B (blue) to the third data line DL3 via the third switching device SW3.
In the LCD device of the related art, the display unit 111, the gate driver 101, data driver 102, and each of the demultiplexers DEMUX1 to DEMUXk to drive the display unit 111 are built into an LCD panel 100. In particular, the data driver 102 of a chip-type is mounted on the LCD panel 100 (e.g., chip on glass “COG”). The timing controller 106 is provided external to the LCD panel 100.
To check whether the image according to the data voltages VD1 to VDk is correctly displayed on each of the pixels, the related art liquid crystal display device further includes a gate line check unit of checking a presence or absence of errors on the gate lines GL1 to GLm and a data line check unit of checking a presence absence of error on the data lines DL1 to DLn. A liquid crystal display device having a gate line check unit and a data line check unit according to the related art is explained in detail as follows.
FIG. 4 shows a block diagram of an LCD device having a gate line check unit and a data line check unit according to the related art. As shown in FIG. 4, an LCD device according to the related art includes of a display unit 111 on which m-gate lines GL1 to GLm and n-data lines DL1 to DLn perpendicularly cross each other to form (m×n) pixels arranged in a matrix form. A TFT is provided at each intersection of the gate and data lines. A gate driver 101 provides a scan pulse voltage SP to the gate lines GL1 to GLm and a data driver (not shown) supplies data voltages VD1 to VDk to the data lines DL1 to DLn of the display unit 111. A plurality of demultiplexers DEMUX1 to DEMUXk is connected between the display unit 111 and the data driver (not shown). A timing controller (not shown) controls the gate driver 101, the data driver (not shown), and the demultiplexers DEMUX1 and DEMUXk. A gate line check unit 403 checks for a presence or absence of errors on the gate lines GL1 to GLm by supplying a test scan pulse voltage VT to the gate lines GL1 to GLm of the display unit 111. A data line check unit 404 checks for a presence or absence of errors on the data lines DL1 to DLn by supplying test data voltages VTR (red), VTG (green), and VTB (blue) to the data lines DL1 to DLn of the display unit 111. In particular, each of the demultiplexers DEMUX1 to DEMUXk has the same configuration of the demultiplexer shown in FIG. 2.
The gate line check unit 403 is connected to one end of each of the gate lines GL1 to GLm and the gate driver 101 is connected to the other end of each of the gate lines GL1 to GLm. Similary, the data line check unit 404 is connected to one end of each of the data lines DL1 to DLn and the data driver 102 is connected to the other end of each of the data lines DL1 to DLn via the demultiplexers DEMUX1 to DEMUXk, respectively.
The gate line check unit 403 includes m-fourth switching devices SW4 supplying the test scan pulse voltage VT to the m-gate lines GL1 to GLm in response to a fourth control signal C4. Namely, one of the fourth switching devices SW4 is connected to one gate line. In particular, gate terminals of the fourth switching devices SW4 are connected in parallel to be supplied with the fourth control signal C4 in common. Drain terminals are individually connected to the gate lines GL1 to GLm, respectively, and source terminals are connected in parallel to be supplied with the test scan pulse voltage VT in common.
The data line check unit 404 includes n-fifth switching devices SW5 supplying the test data voltages VTR, VTG, and VTB to the data lines DL1 to DLn in response to a fifth control signal C5. In particular, gate terminals of the fifth switching devices SW5 are connected parallel to each other to be supplied with the fifth control signal C5 in common. Drain terminals are individually connected to the data lines DL1 to DLn, respectively, and source terminals are supplied with one of the test data voltages VTR, VTG, and VTB.
As previously described, the gate and data line check units 403 and 404 are provided to check whether the gate and data lines GL1 to GLm and DL1 to DLn are in proper operating conditions. When the gate and data line check units 403 and 404 are activated, the gate and data drivers 101 and 102 are deactivated. Specifically, the gate and data line check units 403 and 404 are to temporarily operate the gate and data lines GL1 to GLm and DL1 to DLn before the LCD device is activated by the gate and data drivers 101 and 102 for normal operation. Hence, while the gate and data line check units 403 and 404 are in operation, the gate and data drivers 101 and 102 are disabled. Conversely, during normal operations, the gate and data line check units 403 and 404 are disabled while the gate and data drivers 101 and 102 and the timing controller (not shown) are activated.
The display unit 111, the gate driver 101, the data driver (not shown), the gate line check unit 403, the data line check unit 404, and the demultiplexers DEMUX1 to DEMUXk are built into the LCD panel (not shown). Similar to the description above in relation to FIGS. 1 and 3, the data driver is mounted on the LCD panel in the form of a chip. The timing controller is provided external the LCD panel.
In the related art, the process of checking the gate and data lines GL1 to GLm and DL1 to DLn is carried out prior to loading the data driver 102 and the timing controller 106. Hence, the gate and data drivers 101 and 102 are disabled in the checking process. First, by applying the fourth control signal C4 to the gate line check unit 403, the fourth switching devices SW4 of the gate line check unit 403 are turned on. Once the fourth switching devices SW4 are turned on, each of the fourth switching devices SW4 outputs the test scan pulse voltages VT to the gate lines GL1 to GLm, respectively. Hence, all of the TFTs connected to the gate lines GL1 to GLm become active.
Subsequently, by applying the fifth control signal C5 to the data line check unit 404, the fifth switching devices SW5 of the data line check unit 404 are turned on. Once the fifth switching devices SW5 are turned on, each of the fifth switching devices SW5 outputs one of the test data voltages VTR, VTG, and VTB to the data lines DL1 to DLn. In particular, test R data voltages VTR are supplied to every third data line starting with the first data line DL1, i.e., the first data line DL1, the fourth data line DL4, to the (n−2)th data line DLn−2. Similarly, the test G data voltages VTG are supplied to every third data line starting with the second data line DL2, i.e., the second data line DL2, the fifth data line DL5, to the (n−1)th data line DLn−1. Likewise, the test B data voltages VTB are supplied to every third data line starting with the third data line DL3, i.e., the third data line DL3, the sixth data line DL6, to the nth data line DLn. The test data voltages VTG, VTG, and VTB supplied to the data lines DL1 to DLn are supplied to liquid crystal cells of the pixels via the TFTs turned on by the gate line check unit 403.
In this way, all of the pixels can be tested to display different images according to the test data voltages VTR, VTG, and VTB. In doing so, the success/failure of the gate and data lines GL1 to GLm and DL1 to DLn, i.e., proper connection/disconnection, can be confirmed by checking the abnormality of the picture displayed on the display unit 111. For instance, absence of images horizontally along a certain gate line indicates that the pixels connected to that gate line are not operating. Likewise, absence of images vertically along a certain data line indicates that the pixels connected to that data line are not operating. Moreover, if a specific pixel fails to display an image, such a condition indicates that the TFT connected to that particular pixel is malfunctioning.
In performing the above-explained test process, the first to third switching devices SW1 to SW3 connected to each of the demultiplexers DEMUX1 to DEMUXk need to be prevented from becoming active. If the first to third switching devices SW1 to SW3 are turned on, the active switches SW1 to SW3 create a circuit path between the data lines connected thereto, thereby short-circuiting the data lines DL1 to DLn. In such a case, the test R, G, B data voltages VTR, VTG, and VTB supplied to the data lines DL1 to DLn via the data line check unit 404 become mixed, thereby preventing proper testing of the pixels.
To prevent the first to third switching devices SW1 to SW3 in each of the demultiplexers DEMUX1 to DEMUXk from becoming active during the testing process, a cutoff signal VOFF is supplied to each of the signal input lines IL connected to the gate terminals of the first to third switching devices SW1 to SW3 to maintain their off-states. The cutoff signal VOFF is supplied from an external source by an operator via input terminals 411. The input terminal 411 is connected to one end of each of the signal input lines IL. Because one input terminal is connected to one input line IL, many input terminals 411 are needed to satisfy a large-scale display device with higher resolution.
As the display device becomes larger in scale to achieve higher resolution, the number of the data lines DL1 to DLn increases accordingly. In other words, as the number of the data lines DL1 to DLn increases, the number of the switching devices in the demultiplexers DEMUX1 to DEMUXk increases. As the number of the switching devices increases, the corresponding number of the input terminals 411 increases as well. Since the input terminals 411 are formed on the LCD panel 100, an area for accommodating the input terminals 411 increases in size to accommodate the increased number of input terminals 411. Hence, the increasing number of the input terminals 411 contravenes the effort to reduce the size of the LCD panel. Moreover, because the fourth control signal C4, the test scan pulse voltage VT, the fifth control signal C5, and the test data voltages VTR, VTG, and VTB are all provided from an external source, additional input terminals (not shown in the drawing) needed for inputting these signals and voltages also contribute to the size reduction problem.